Description:
The ADCLK946BCPZ is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter.
The device has a differential input equipped with center-tapped, differential, 100 Ω on-chip termination resistors. The input accepts dc-coupled LVPECL, CML, 3.3 V CMOS (single ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREF pin is available for biasing ac-coupled inputs.
The ADCLK946BCPZ features six full-swing emitter-coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply.
The ECL output stages are designed to directly drive 800 mV each side into 50 Ω terminated to VCC − 2 V for a total differen-tial output swing of 1.6 V.
Features：
4.8 GHz operating frequency
75 fs rms broadband random jitter
On-chip input terminations
3.3 V power supply
Applications:
Communication systems: such as wireless base stations, fiber optic communication systems, satellite communication, etc.
Data converter: clock source for high-speed data converters such as ADC, DAC, etc.
Clock generator: provides a highly stable clock signal for the system.
Instrumentation: Instruments such as oscilloscopes, signal generators, etc. that require high stability timing clock sources.
FUNCTIONAL DESCRIPTION
CLOCK INPUTS
The ADCLK946 accepts a differential clock input and distributes it to all six LVPECL outputs.
The maximum specified frequency is the point at which the output voltage swing is 50% of the standard LVPECL swing.
The device has a differential input equipped with center-tapped, differential, 100 Ω on-chip termination resistors.
The input accepts dc-coupled LVPECL, CML, 3.3 V CMOS (single ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs.
A VREF pin is available for biasing ac-coupled inputs.
Maintain the differential input voltage swing from approximately 400 mV p-p to no more than 3.4 V p-p.For various clock input termination schemes.
Output jitter performance is degraded by an input slew rate below 1 V/ns.
The ADCLK946 is specifically designed to minimize added random jitter over a wide input slew rate range.
Whenever possible, clamp excessively large input signals with fast Schottky diodes because attenuators reduce the slew rate.
Input signal runs of more than a few centimeters should be over low loss dielectrics or cables with good high frequency characteristics.
CLOCK OUTPUTS
The specified performance necessitates using proper transmission line terminations.
The LVPECL outputs of the ADCLK946 are designed to directly drive 800 mV into a 50 Ω cable or into microstrip/stripline transmission lines terminated with 50 Ω referenced to VCC − 2 V.
The outputs are designed for best transmission line matching.
If high speed signals must be routed more than a centimeter, either the microstrip or the stripline technique is required to ensure proper transition times and to prevent excessive output ringing and pulse-width-dependent, propagation delay dispersion.
Thevenin-equivalent termination uses a resistor network to provide 50 Ω termination to a dc voltage that is below VOL of the LVPECL driver. In this case, VS_DRV on the ADCLK946 should equal VCC of the receiving buffer. Although the resistor combination shown in Figure 15 results in a dc bias point of VS_DRV − 2 V, the actual common-mode voltage is VS_DRV − 1.3 V because there is additional current flowing from the
ADCLK946 LVPECL driver through the pull-down resistor. LVPECL Y-termination is an elegant termination scheme that uses the fewest components and offers both odd- and even-mode impedance matching. Even-mode impedance matching is an important consideration for closely coupled transmission lines at high frequencies. Its main drawback is that it offers limited flexibility for varying the drive strength of the emitter-follower LVPECL driver. This can be an important consideration when driving long trace lengths but is usually not an issue.
