Description:

The Intel® Intel Cyclone® 10 LP FPGAs are optimized for low cost and low static power, making them ideal for high-volume and cost-sensitive applications.

Intel Cyclone 10 LP devices provide a high density sea of programmable gates, on board resources, and general purpose I/Os. These resources satisfies the requirements of I/O expansion and chip-to-chip interfacing. The Intel Cyclone 10 LP architecture suits smart and connected end applications across many market segments:

  • Industrial and automotive
  • Broadcast, wireline, and wireless
  • Compute and storage
  • Government, military, and aerospace
  • Medical, consumer, and smart energy

The free but powerful Intel Quartus® Prime Lite Edition software suite of design tools meets the requirements of several classes of users:

  • Existing FPGA designers
  • Embedded designers using the FPGA with Nios® II processor
  • Students and hobbyists who are new to FPGA

Advanced users who require access to the full IP Base Suite can subscribe to the Intel Quartus Prime Standard Edition or purchase the license separately.

 

Features：

Technology

  • Low-cost, low-power FPGA fabric
  • 1.0 V and 1.2 V core voltage options
  • Available in commercial, industrial, and automotive temperature grades

Packaging

  • Several package types and footprints:

— FineLine BGA (FBGA)

— Enhanced Thin Quad Flat Pack (EQFP)

— Ultra FineLine BGA (UBGA)

— Micro FineLine BGA (MBGA)

  • Multiple device densities with pin migration capability
  • RoHS6 compliance

Core architecture

  • Logic elements (LEs)—four-input look-up table (LUT) and register
  • Abundant routing/metal interconnect between all Les

Internal memory blocks

  • M9K—9-kilobits (Kb) of embedded SRAM memory blocks, cascadable
  • Configurable as RAM (single-port, simple dual port, or true dual port), FIFO buffers, or ROM

Embedded multiplier blocks

  • One 18 × 18 or two 9 × 9 multiplier modes, cascadable
  • Complete suite of DSP IPs for algorithmic acceleration

Clock networks

  • Global clocks that drive throughout entire device, feeding all device quadrants
  • Up to 15 dedicated clock pins that can drive up to 20 global clocks

Phase-locked loops (PLLs)

  • Up to four general purpose PLLs
  • Provides robust clock management and synthesis

General-purpose I/Os (GPIOs)

  • Multiple I/O standards support
  • Programmable I/O features
  • True LVDS and emulated LVDS transmitters and receivers
  • On-chip termination (OCT)

SEU mitigation

SEU detection during configuration and operation

Configuration

  • Active serial (AS), passive serial (PS), fast passive parallel (FPP)
  • JTAG configuration scheme
  • Configuration data decompression
  • Remote system upgrade

 

Applications:

Industrial and automotive
Broadcast, wireline, and wireless
Compute and storage
Government, military, and aerospace
Medical, consumer, and smart energy

 

Logic Elements and Logic Array Blocks

The LAB consists of 16 logic elements (LE) and a LAB-wide control block. An LE is the smallest unit of logic in the Intel Cyclone 10 LP device architecture. Each LE has four inputs, a four-input look-up table (LUT), a register, and output logic. The four-input LUT is a function generator that can implement any function with four variables.

 

Embedded Multipliers

Each embedded multiplier block in Intel Cyclone 10 LP devices supports one individual 18 × 18-bit multiplier or two individual 9 × 9-bit multipliers. You can cascade the multiplier blocks to form wider or deeper logic structures.

You can control the operation of the embedded multiplier blocks using the following options:

  • Parameterize the relevant IP cores with the Intel Quartus Prime parameter editor
  • Infer the multipliers directly with VHDL or Verilog HDL

Intel and partners offer popular DSP IPs for Intel Cyclone 10 LP devices, including:

  • Finite impulse response (FIR)
  • Fast Fourier transform (FFT)
  • Numerically controlled oscillator (NCO) functions

For a streamlined DSP design flow, the DSP Builder tool integrates the Intel Quartus Prime software with MathWorks Simulink and MATLAB design environments.